In the integrated circuit (IC) industry, metal-oxide-semiconductor (MOS) transistors have typically been formed utilizing polysilicon gate electrodes. Polysilicon material is typically preferred for use as an MOS gate electrode due to its thermal resistive properties (i.e., polysilicon can better withstand subsequent high temperature processing). Polysilicon's robustness during high temperature processing allows polysilicon to be high-temperature annealed along with source and drain regions. Furthermore, polysilicon's ability to block the ion implantation of dopant atoms into a channel region is advantageous. Due to the ion implantation blocking potential of polysilicon, polysilicon allows for the easy formation of self-aligned source and drain structures after gate patterning is completed.
However, polysilicon gate electrodes suffer from several disadvantages. First, polysilicon requires the ion implantation of different dopant atoms for p-channel transistors and n-channel transistors formed in a surface CMOS process. These different dopant atom species of the polysilicon gate electrodes are required in order to get the p-channel and n-channel transistors of a CMOS process to have compatible threshold voltages (V.sub.t). Furthermore, most MOS transistors formed using a polysilicon gate technology require a threshold (V.sub.t) adjust implant into the MOS channel region. This threshold adjust implant is of a high enough doping concentration to adversely impact the mobility of carriers through the channel region. Polysilicon gate electrodes are semiconductor materials that suffer from higher resistivities than most metal materials. Therefore, polysilicon materials operate at a much slower speed than metallic materials. To compensate for this higher resistance, polysilicon materials require extensive and expensive silicide processing in order to increase their speed of operation to acceptable levels. Furthermore, polysilicon materials suffer from a polysilicon depletion phenomenon whereby the effective gate oxide thickness (EOT) of polysilicon transistors is increased by polysilicon depletion. Also, polysilicon gate electrodes are sometimes disadvantageous due to lack of threshold voltage control when utilized in fully depleted silicon-on-insulator (SOI) structures.
Therefore, a need exists in the industry for a metal gate process which can replace polysilicon gate devices. However, metal gates cannot withstand the higher temperatures and oxidation ambients which can be withstood by conventional polysilicon gate electrodes. In addition, metal films cannot effectively block ion implantation of dopant atoms into a channel region whereby self-aligned source and drain electrodes cannot be readily formed using conventional implant processing when a metal gate is used. In addition, some metal films will not adequately adhere to surrounding layers when these metal materials are patterned to small geometries. Some metal films are difficult to lithographically pattern and etch via conventional processing due to the fact that the etching of these metal films may significantly damage underlying oxides thereby affecting device performance. Furthermore, through subsequent thermal processing of the integrated circuit (IC), instability and degradation of the gate oxide may occur due to chemical interaction between the metal and oxide at the metal-gate-to-gate-oxide interface.
Therefore, a need exists for a process which can be utilized to form a self-aligned MOS transistor having metal gate electrodes.